[CAAQA] CH01A - Components of Computer Architecture
Motivation for Computers
- some contraption needed to do what humans can do
- at the top lies the actual Application
- at the bottom lies the Physics of reality
- this gap is too large to fill in one single step
- in between them lie the abstraction and implementation layers that need be designed and manufactured or programmed
fig: Computer Architecture (Highlighted Layers) in the Computer Technology Stack
Computer Architecture
- in the broadest sense
- Computer Architecture: design of abstraction and implementation layers that allows execution of information processing applications efficiently using manufacturing technologies
Classes of Computers
Class | Price of System | Price of Microprocessor | Design Issues |
---|---|---|---|
Personal Mobile Device (PMD) | USD100 - USD1000 | USD10 - USD100 | Cost, Energy, Media Performance, Responsiveness |
Desktop | USD300-USD2500 | USD50 - USD500 | Price-Performance, Energy, Graphics-Performance |
Server | USD5000 - USD10000000 | USD20 - USD2000 | Price-Performance, Throughput,Energy Proportionality |
Clusters/Warehouse-Scale Computers(WSC) | USD100000 - USD200000000 | USD50 - USD250 | |
Internet of Things/Embedded Computers | USD10 - USD100000 | USD0.01 - USD100 | Price, Energy, Application-Specific-Performance |
Classes of Parallelism
- parallelism is what’s hot!
- the driving force of computer design across all classes of computers
- energy and cost are constraints
Application Level Parallelism
- Data-Level Parallelism (DLP)
- many data items can be operated at the same time
- Task-Level Parallelism (TLP)
- many sub tasks for the work to be done can be operated on independently and largely in parallel
Hardware Level Parallelism
- Instruction-Level Parallelism
- exploits DLP using pipelining and speculative execution
- Vector Architectures, Graphic Processor Units (GPUs), Multimedia Instruction Sets
- exploits DLP by applying single instruction to a collection of data in parallel
- Thread-Level Parallelism
- exploits DLP or TLP in a tightly coupled hardware model which allows interaction between parallel threads
- Request-Level Parallelism
- exploits parallelism among largely decoupled tasks specified by the programmer or OS
Parallel Architectures
- SISD: single instruction stream, single data stream
- uniprocessor architecture, can still exploit Instruction Level Parallelism
- SIMD: single instruction stream, multiple data streams
- same instruction is executed by multiple processors using different data streams
- each processor has its own data memory
- single instruction memory and control processor that fetches and dispatches instructions
- same instruction is executed by multiple processors using different data streams
- MISD: multiple instruction streams, single data stream
- no commercial multiprocessor of this type
- MIMD: multiple instruction streams, multiple data streams
- each processor fetches its own instruction and operates on its own data
- targets TLP
- more flexible than SIMD, but more expensive as well
- two kinds of MIMD:
- tightly coupled MIMD:
- multiple co-operating threads operate in parallel, using thread-level parallelism
- loosely coupled MIMD:
- exploits request-level parallelism, where many independent tasks can proceed naturally in parallel with little need for communication or sync
- applicable to clusters and warehouse-scale computers
- tightly coupled MIMD:
- each processor fetches its own instruction and operates on its own data
Defining Computer Architecture
- computer architecture = ISA + Micro-Architecture + Hardware
Computer Architecture Design Goals
- problem statement
- what attributes are important for a new computer?
- typical goals of design a computer
- to maximize
- performance
- cost
- staying within
- cost
- power
- availability constraints
- to maximize
- the actual requirements for computer design maybe specific features inspired by the market
- application software typically drives the choice of certain functional requirements
- support for ISA influences the selection of ISA chosen for the overall architecture
- the large market for a specific application might make designers make the computer competitive in that market
Aspects of COmputer Architecture Design
- designing a computer has many aspects
- instruction set design (Instruction Set Architecture)
- functional organization
- logic design
- logic implementation
- IC design, packaging, power and cooling
- optimizing design requires familiarity with wide range of technologies
- from compilers and OS to logic design and packaging
ISA (Instruction Set Architecture)
- the actual programmer-visible instruction set
- boundary between hardware and software
RISC-V (RISC Five)
- RISC: Reduced Instruction Set Architecture
- RISC Five is a modern RISC based instruction set
- 30 years later from RISC
- freely and openly adoptable
- provides full software stack
- compilers
- OS
- simulators
- several implementations of RISC-V available freely for custom chips or FPGAs (Field Programmable Gate Arrays)
Seven Dimensions of ISA
- Class of ISA: General Purpose Register Architectures
- register-memory ISA: can access memory as a part of many operations
- load-store ISA: can access memory only for load-store operations
- Memory Addressing: byte addressing
- aligned-objects:
- object of size \(s\) bytes at byte address \(A\) is aligned if \( A \text{ }modulo\text{ } s = 0 \)
- RISC-V does not required aligned, but access is generally faster if operands are aligned
- aligned-objects:
- Addressing Modes:
- in addition to specifying registers and constant operands, addressing mode specifies the address of a memory object
- RISC-V has three kinds of addressing modes:
- Register
- Immediate
- Displacement
- Types and Side of Operands:
- 8-bit (ASCII Char)
- 16-bit (Unicode Char or Half Words)
- 32-bit (Integer of Full Word)
- 64-bit (Double Word or Long Integer)
- 32-bit IEEE 754 floating point (Single Precision)
- 62-bit IEEE 754 floating point (Double Precision)
- Operations:
- general categories are:
- data transfer,
- arithmetic logic
- control
- floating point
- RISC-V is a simple and easy-to-pipeline ISA
- general categories are:
- Control Flow Instructions:
- RICS-V supports following operations:
- conditional branches
- unconditional jumps
- procedure calls
- returns
- RISC-V used PC-relative addressing, where the branch address if specified by an address field that is added to the PC
- RISC-V conditional branches tests the registers
- RISC-V procedure calls places the return address in a register
- RICS-V supports following operations:
- Encoding an ISA:
- two basic types of ISA encoding:
- fixed length
- variable length
- RISC-V instructions are 32-bits long (fixed-length)
- simplifies instruction decoding
- variable length instructions programs usually take less space than fixed length ones
- RISC-V extension EV64IC offers an extension ISA that provides a mix of 16-bit and 32-bit instruction to reduce program size
- two basic types of ISA encoding:
RISC-V ISA Formats
fig: RISC-V ISA Formats
- R format:
- for integer register-to-register operations such as ADD, SUB etc
- I format:
- for loads and immediate operations such as LD and ADDI
- B format:
- for branches
- S format:
- for stores (allows the register specifiers to always be the same location for all formats)
- U format:
- for wide immediate instructions
- J format:
- jumps and link
Micro-Architecture
- after the ISA, this is the next layer of implementation of the computer architecture
- also called organization of a computer, this layer includes the high-level aspects of a computer’s design
- the memory system
- memory interconnect
- design of the internal processor
- processor terminology:
- core: processor
- multicore: multiprocessor microprocessor
- the term CPU is fading away because of the multicore paradigm
Hardware
- the actual specifics of the computer including
- detailed logic design
- packaging technology of the computer